1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
High density memory devices are being designed that comprise arrays of flash memory cells, or other types of memory cells. In some examples, the memory cells comprise thin film transistors which can be arranged in 3D architectures.
In one example, a 3D memory device includes a plurality of stacks of NAND strings of memory cells. The stacks include active strips separated by insulating material. The 3D memory device includes an array including a plurality of word line structures, a plurality of string select structures, and ground select lines, arranged orthogonally over the plurality of stacks. Memory cells including charge storage structures are formed at cross-points between side surfaces of the active strips in the plurality of stacks and the word lines structures. Array arrangement for array elements including string select structures can affect array efficiency, and/or on/off characteristics for the stacks of NAND strings of 3D memory devices.
One 3D memory device uses finger VG (vertical gates), and has relatively low array efficiency because it uses two sets of SSL gate structures, two horizontal ground select lines, and two sets of ground contacts. Another 3D memory device uses IDG (independent double gates), and has higher array efficiency because it uses one set of SSL gate structures instead of two, one horizontal ground select line instead of two, and one ground line instead of two sets of ground contacts. But the second 3D memory device exhibits relatively poor current on/off characteristics.
Related U.S. patent application Ser. No. 13/887,019 shows one approach, in which IDGs control conductivity at one end of the stacks of NAND strings of memory cells. In this approach, one independent gate is positioned in between each adjacent pair of stacks of NAND strings of memory cells. Because of this substantially one-to-one numerical correspondence between the number of independent gates and the number of stacks of NAND strings of memory cells, the pitch requirements on contacts of the independent gates are relatively strict.
Another approach is a “twisted” selection structure arrangement, in which adjacent selection structures are staggered along the lengths of the stacks of NAND strings of memory cells at the same end of the stacks. Although such an arrangement has relatively relaxed pitch requirements on the contacts of the “twisted” selection structures, the staggering requires more space along the lengths of the stacks of NAND strings of memory cells.
It is desirable to provide a structure for three-dimensional integrated circuit memory with higher array efficiency, and improved on/off characteristics for the stacks of NAND strings.